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SN74LS74AN

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Texas Instruments

DUAL D-TYPE POS.-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

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PDIP (N)
Integrated Circuits (ICs)

SN74LS74AN

Active
Texas Instruments

DUAL D-TYPE POS.-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LS74AN
Clock Frequency33 MHz
Current - Output High, Low [custom]400 µA
Current - Output High, Low [custom]8 mA
Current - Quiescent (Iq)8 mA
FunctionReset, Set(Preset)
Max Propagation Delay @ V, Max CL25 ns
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeComplementary
Package / Case14-DIP
Package / Case [x]0.3 "
Package / Case [y]7.62 mm
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.21
10$ 0.76
25$ 0.64
100$ 0.50
250$ 0.44
500$ 0.40
1000$ 0.36
2500$ 0.32
5000$ 0.30
Texas InstrumentsTUBE 1$ 0.57
100$ 0.39
250$ 0.30
1000$ 0.20

Description

General part information

SN74LS74A Series

These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.

These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.