Specification	SN74LVC2G79DCURG4

Clock Frequency	160 MHz
Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	5 µA
Function	Standard
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	4.5 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted
Package / Case	8-VFSOP
Package / Case [y]	2.3 mm
Package / Case [y]	0.091 in
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC2G79 Series

Dual Positive-Edge-Triggered D-Type Flip-Flop

Part	Output Type	Current - Quiescent (Iq)	Clock Frequency	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [y]	Current - Output High, Low [x]	Max Propagation Delay @ V, Max CL	Number of Elements	Function	Type	Mounting Type	Input Capacitance	Package / Case	Number of Bits per Element	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]	Operating Temperature [Max]	Operating Temperature [Min]	Trigger Type	Package / Case [y]	Package / Case [y]
Texas Instruments SN74LVC2G79YEPR	Non-Inverted	5 µA	160 MHz	5.5 V	1.65 V	32 mA	32 mA	4.5 ns	2	Standard	D-Type	Surface Mount	3.5 pF	8-XFBGA DSBGA	1	0.9	8-DSBGA (1.9x0.9)	1.9	85 °C	-40 °C	Positive Edge
Texas Instruments SN74LVC2G79YZPR	Non-Inverted	5 µA	160 MHz	5.5 V	1.65 V	32 mA	32 mA	4.5 ns	2	Standard	D-Type	Surface Mount	3.5 pF	8-XFBGA DSBGA	1		8-DSBGA		85 °C	-40 °C	Positive Edge
Texas Instruments SN74LVC2G79DCURG4	Non-Inverted	5 µA	160 MHz	5.5 V	1.65 V	32 mA	32 mA	4.5 ns	2	Standard	D-Type	Surface Mount	3.5 pF	8-VFSOP	1				125 °C	-40 °C	Positive Edge	2.3 mm	0.091 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	3000	$ 0.30
		6000	$ 0.28
		15000	$ 0.27
		30000	$ 0.26
Texas Instruments	LARGE T&R	1	$ 0.51
		100	$ 0.39
		250	$ 0.29
		1000	$ 0.20

Description

General part information

SN74LVC2G79 Series

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Documents

Technical documentation and resources

SN74LVC2G79DCURG4

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SN74LVC2G79DCURG4

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Technical Specifications

SN74LVC2G79 Series

Pricing

Description

SN74LVC2G79 Series

Documents

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Signal Switch Data Book (Rev. A)

Selecting the Right Level Translation Solution (Rev. A)

How to Select Little Logic (Rev. A)

Simplifying Solid-State Relay Designs With Logic

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Standard Linear & Logic for PCs, Servers & Motherboards

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Power-Up Behavior of Clocked Devices (Rev. B)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

LVC Characterization Information

Low-Voltage Logic (LVC) Designer's Guide

Input and Output Characteristics of Digital Integrated Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

Texas Instruments Little Logic Application Report

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Live Insertion

Dual Positive-Edge-Triggered D-Type Flip-Flop, SN74LVC2G79 datasheet (Rev. E)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Logic Guide (Rev. AB)

Design Summary for WCSP Little Logic (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Little Logic Guide 2018 (Rev. G)

Understanding Advanced Bus-Interface Products Design Guide

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

LOGIC Pocket Data Book (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

SN74LVC2G79 Series