Zenode.ai Logo
Beta
10-TFSOP, 10-MSOP
Integrated Circuits (ICs)

SY88933VKG-TR

Active
Microchip Technology

3.3V-5.0V 1.25GBPS PECL POST AMP 10 MSOP 3X3X1.0MM T/R ROHS COMPLIANT: YES

Deep-Dive with AI

Search across all available documentation for this part.

10-TFSOP, 10-MSOP
Integrated Circuits (ICs)

SY88933VKG-TR

Active
Microchip Technology

3.3V-5.0V 1.25GBPS PECL POST AMP 10 MSOP 3X3X1.0MM T/R ROHS COMPLIANT: YES

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSY88933VKG-TR
ApplicationsOptical Networks
Mounting TypeSurface Mount
Package / Case10-MSOP, 10-TFSOP
Package / Case [x]3 mm
Package / Case [x]0.118 in
Supplier Device Package10-MSOP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 9.65
Tape & Reel (TR) 1000$ 7.30
Microchip DirectT/R 1$ 9.65
25$ 8.03
100$ 7.30
1000$ 6.08
5000$ 5.63
10000$ 5.21
NewarkEach (Supplied on Full Reel) 100$ 7.52

Description

General part information

SY88933AL Series

The SY88933AL high-sensitivity limiting post amplifier is designed for use in fiber-optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88933AL quantizes these signals and outputs PECL level waveforms.

The SY88933AL operates from a single +3.3V power supply, over temperatures ranging from -40°C to +8°C. With its wide bandwidth and high gain, signal with data rates up to 1.25Gbps and as small as 5mVPP can be amplified to drive devices with PECL inputs.

The SY88933AL generates a high gain signal-detect (SD) open-collector TTL output. The SD function has a high gain input stage for increased sensitivity. A programmable signal-detect level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and de-asserts low otherwise. The enable input (EN) de-asserts the true output signal without removing the input signal. The SD output can be fed back to the EN input to maintain output stability under a loss-of-signal condition. Typically, 3.4dB SD hysteresis is provided to prevent chattering.

Documents

Technical documentation and resources