Specification	SN74HC109N

Clock Frequency	60 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	4 çA
Function	Reset, Set(Preset)
Input Capacitance	3 pF
Mounting Type	Through Hole
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	0.3 in
Package / Case	16-DIP
Package / Case	7.62 mm
Supplier Device Package	16-PDIP
Trigger Type	Positive Edge
Type	JK Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

CD74HC109 Series

High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

Part	Type	Package / Case	Package / Case [x]	Package / Case [y]	Function	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Supplier Device Package	Input Capacitance	Trigger Type	Current - Quiescent (Iq)	Number of Elements	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Output Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case
Texas Instruments CD74HC109M96	JK Type	16-SOIC	0.154 in	3.9 mm	Reset Set(Preset)	125 °C	-55 °C	60 MHz	16-SOIC	10 pF	Positive Edge	4 çA	2	Surface Mount	2 V	6 V	Complementary	5.2 mA	5.2 mA	1
Texas Instruments SN74HC109NG4	JK Type	16-DIP			Reset Set(Preset)			60 MHz	16-PDIP	3 pF	Positive Edge	4 çA	2	Through Hole	2 V	6 V	Complementary	5.2 mA	5.2 mA	1	85 °C	-40 °C	0.3 in	7.62 mm
Texas Instruments CD74HC109M	JK Type	16-SOIC	0.154 in	3.9 mm	Reset Set(Preset)	125 °C	-55 °C	60 MHz	16-SOIC	10 pF	Positive Edge	4 çA	2	Surface Mount	2 V	6 V	Complementary	5.2 mA	5.2 mA	1
Texas Instruments SN74HC109NSR	JK Type	16-SOIC			Reset Set(Preset)			60 MHz	16-SO	3 pF	Positive Edge	4 çA	2	Surface Mount	2 V	6 V	Complementary	5.2 mA	5.2 mA	1	85 °C	-40 °C	0.209 "	5.3 mm
Texas Instruments SN74HC109NSRE4	JK Type	16-SOIC			Reset Set(Preset)			60 MHz	16-SO	3 pF	Positive Edge	4 çA	2	Surface Mount	2 V	6 V	Complementary	5.2 mA	5.2 mA	1	85 °C	-40 °C	0.209 "	5.3 mm
Texas Instruments SN74HC109N	JK Type	16-DIP			Reset Set(Preset)			60 MHz	16-PDIP	3 pF	Positive Edge	4 çA	2	Through Hole	2 V	6 V	Complementary	5.2 mA	5.2 mA	1	85 °C	-40 °C	0.3 in	7.62 mm
Texas Instruments SN74HC109DT	JK Type	16-SOIC	0.154 in	3.9 mm	Reset Set(Preset)			60 MHz	16-SOIC	3 pF	Positive Edge	4 çA	2	Surface Mount	2 V	6 V	Complementary	5.2 mA	5.2 mA	1	85 °C	-40 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Arrow	N/A	1	$ 0.90
		10	$ 0.65
		50	$ 0.58
		100	$ 0.51
		200	$ 0.49
Digikey	Tube	1	$ 0.85
		10	$ 0.76
		25	$ 0.72
		100	$ 0.59
		250	$ 0.55
		500	$ 0.49
		1000	$ 0.39
		2500	$ 0.36
		5000	$ 0.34
Texas Instruments	TUBE	1	$ 0.94
		100	$ 0.64
		250	$ 0.49
		1000	$ 0.33

Description

General part information

CD74HC109 Series

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

Documents

Technical documentation and resources

SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. C)

Data sheet

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

SN74HC109N

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SN74HC109N

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Technical Specifications

CD74HC109 Series

Pricing

Description

CD74HC109 Series

Documents

LOGIC Pocket Data Book (Rev. B)

Live Insertion

SN54/74HCT CMOS Logic Family Applications and Restrictions

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

CMOS Power Consumption and CPD Calculation (Rev. B)

Logic Guide (Rev. AB)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Signal Switch Data Book (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Designing With Logic (Rev. C)

TI IBIS File Creation, Validation, and Distribution Processes

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. C)

Power-Up Behavior of Clocked Devices (Rev. B)

CD74HC109 Series