Specification	SN74LVC1G74DCUR

Clock Frequency	200 MHz
Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	10 µA
Function	Reset, Set(Preset)
Input Capacitance	5 pF
Max Propagation Delay @ V, Max CL	6.4 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	8-VFSOP
Package / Case [y]	2.3 mm
Package / Case [y]	0.091 in
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC1G74 Series

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset

Part	Input Capacitance	Output Type	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Elements	Max Propagation Delay @ V, Max CL	Function	Current - Quiescent (Iq)	Trigger Type	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Type	Package / Case	Supplier Device Package	Clock Frequency	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case [y]	Package / Case [y]
Texas Instruments SN74LVC1G74DQER	5 pF	Complementary	32 mA	32 mA	1	4.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-XFDFN	8-X2SON (1.4x1)	200 MHz	1	-40 °C	125 °C
Texas Instruments SN74LVC1G74DCUR	5 pF	Complementary	32 mA	32 mA	1	6.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-VFSOP		200 MHz	1	-40 °C	125 °C	2.3 mm	0.091 in
Texas Instruments SN74LVC1G74RSER	5 pF	Complementary	32 mA	32 mA	1	4.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-UFQFN	8-UQFN (1.5x1.5)	200 MHz	1	-40 °C	85 °C
Texas Instruments SN74LVC1G74RSE2	5 pF	Complementary	32 mA	32 mA	1	4.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-UFQFN	8-UQFN (1.5x1.5)	200 MHz	1	-40 °C	85 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.53
		10	$ 0.45
		25	$ 0.42
		100	$ 0.34
		250	$ 0.31
		500	$ 0.26
		1000	$ 0.20
	Digi-Reel®	1	$ 0.53
		10	$ 0.45
		25	$ 0.42
		100	$ 0.34
		250	$ 0.31
		500	$ 0.26
		1000	$ 0.20
	Tape & Reel (TR)	3000	$ 0.19
		6000	$ 0.17
		15000	$ 0.16
		30000	$ 0.15
Texas Instruments	LARGE T&R	1	$ 0.30
		100	$ 0.21
		250	$ 0.16
		1000	$ 0.11

Description

General part information

SN74LVC1G74 Series

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Documents

Technical documentation and resources

SN74LVC1G74DCUR

Deep-Dive with AI

SN74LVC1G74DCUR

Deep-Dive with AI

Technical Specifications

SN74LVC1G74 Series

Pricing

Description

SN74LVC1G74 Series

Documents

Power-Up Behavior of Clocked Devices (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

How to Select Little Logic (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Little Logic Guide 2018 (Rev. G)

Logic Guide (Rev. AB)

Selecting the Right Level Translation Solution (Rev. A)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Texas Instruments Little Logic Application Report

TI IBIS File Creation, Validation, and Distribution Processes

Standard Linear & Logic for PCs, Servers & Motherboards

Design Summary for WCSP Little Logic (Rev. B)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

LOGIC Pocket Data Book (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset datasheet (Rev. G)

Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A)

Simplifying Solid-State Relay Designs With Logic

LVC Characterization Information

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Signal Switch Data Book (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Live Insertion

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Low-Voltage Logic (LVC) Designer's Guide

SN74LVC1G74 Series