SN74LVC1G74 Series

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset

Part	Input Capacitance	Output Type	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Elements	Max Propagation Delay @ V, Max CL	Function	Current - Quiescent (Iq)	Trigger Type	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Type	Package / Case	Supplier Device Package	Clock Frequency	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case [y]	Package / Case [y]
Texas Instruments SN74LVC1G74DQER	5 pF	Complementary	32 mA	32 mA	1	4.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-XFDFN	8-X2SON (1.4x1)	200 MHz	1	-40 °C	125 °C
Texas Instruments SN74LVC1G74DCUR	5 pF	Complementary	32 mA	32 mA	1	6.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-VFSOP		200 MHz	1	-40 °C	125 °C	2.3 mm	0.091 in
Texas Instruments SN74LVC1G74RSER	5 pF	Complementary	32 mA	32 mA	1	4.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-UFQFN	8-UQFN (1.5x1.5)	200 MHz	1	-40 °C	85 °C
Texas Instruments SN74LVC1G74RSE2	5 pF	Complementary	32 mA	32 mA	1	4.4 ns	Reset Set(Preset)	10 µA	Positive Edge	Surface Mount	5.5 V	1.65 V	D-Type	8-UFQFN	8-UQFN (1.5x1.5)	200 MHz	1	-40 °C	85 °C

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset

Key Features

• Available in the Texas Instruments NanoFree™ packageSupports 5-V VCCoperationInputs accept voltages to 5.5-VSupports down translation to VCCMaximum tpdof 5.9-ns at 3.3-VLow power consumption, 10-µA maximum ICC±24-mA output drive at 3.3-VTypical VOLP(output ground bounce) < 0.8-V at VCC= 3.3-V, TA= 25°CTypical VOHV(output VOHundershoot) > 2-V at VCC= 3.3 V, TA= 25°CIoffsupports live insertion, partial-power-down mode, and back-drive protectionLatch-up performance exceeds 100 mA per JESD 78, class IIESD protection exceeds JESD 222000-V human-body model200-V machine model1000-V charged-device modelAvailable in the Texas Instruments NanoFree™ packageSupports 5-V VCCoperationInputs accept voltages to 5.5-VSupports down translation to VCCMaximum tpdof 5.9-ns at 3.3-VLow power consumption, 10-µA maximum ICC±24-mA output drive at 3.3-VTypical VOLP(output ground bounce) < 0.8-V at VCC= 3.3-V, TA= 25°CTypical VOHV(output VOHundershoot) > 2-V at VCC= 3.3 V, TA= 25°CIoffsupports live insertion, partial-power-down mode, and back-drive protectionLatch-up performance exceeds 100 mA per JESD 78, class IIESD protection exceeds JESD 222000-V human-body model200-V machine model1000-V charged-device model

Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.