ADC12DJ5200SEAAV
ActiveSINGLED-ENDED INPUT RF-SAMPLING 12-BIT ADC WITH DUAL-CHANNEL 5.2 GSPS OR SINGLE-CHANNEL 10.4 GSPS
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ADC12DJ5200SEAAV
ActiveSINGLED-ENDED INPUT RF-SAMPLING 12-BIT ADC WITH DUAL-CHANNEL 5.2 GSPS OR SINGLE-CHANNEL 10.4 GSPS
Technical Specifications
Parameters and characteristics for this part
| Specification | ADC12DJ5200SEAAV |
|---|---|
| Architecture | Pipelined, SAR |
| Configuration | MUX-ADC |
| Data Interface | JESD204B, JESD204C |
| Input Type | Single Ended, Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Bits | 12 bits |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | FCBGA, 144-FBGA |
| Ratio - S/H:ADC | 0:2 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 5.2 G |
| Supplier Device Package | 144-FCBGA (10x10) |
| Voltage - Supply, Analog [Max] | 2 V, 1.15 V |
| Voltage - Supply, Analog [Min] | 1.8 V, 1.05 V |
| Voltage - Supply, Digital [Max] | 1.15 V |
| Voltage - Supply, Digital [Min] | 1.05 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 184 | $ 3045.70 | |
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 2186.40 | |
| 100 | $ 2004.20 | |||
| 250 | $ 1894.88 | |||
| 1000 | $ 1822.00 | |||
Description
General part information
ADC12DJ5200SE Series
The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3dB input frequency range of 2 to 6.3GHz enables direct RF sampling of S-band and C-band for frequency agile systems.
The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
Documents
Technical documentation and resources