ADC12DJ5200SE Series

Singled-ended input RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Catalog

Singled-ended input RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Part	Number of Bits	Package / Case	Input Type	Number of Inputs	Architecture	Data Interface	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Number of A/D Converters	Ratio - S/H:ADC	Configuration	Supplier Device Package	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Sampling Rate (Per Second)	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Reference Type
Texas Instruments ADC12DJ5200SEAAV	12 bits	144-FBGA FCBGA	Differential Single Ended	2	Pipelined SAR	JESD204B JESD204C	1.15 V	1.05 V	2	0:2	MUX-ADC	144-FCBGA (10x10)	Surface Mount	85 °C	-40 °C	5.2 G	1.05 V 1.8 V	1.15 V 2 V	External Internal

Catalog

Singled-ended input RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Key Features

• ADC core:12-bit resolutionUp to 10.4GSPS in single-channel modeUp to 5.2GSPS in dual-channel modeSingle Ended 50Ω Inputs:Analog input range (–3dB): 2 to 6.3GHzFull-scale input power (4.5GHz): - 1.25dBmFlexible VCM: AC coupled with no DC path to GND or supplyPerformance specifications:Noise floor (2.3GHz, –20dBFS,INPUTFS = 1.5dBm):Dual-channel mode: –149dBFS/HzSingle-channel mode: –151.5dBFS/HzENOB (dual channel, FIN = 2.3GHz): 8.5 BitsNoiseless aperture delay (tAD) adjustment:Precise sampling control: 19fs StepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingJESD204C serial data interface:Maximum lane rate: 17.16GbpsSupport for 64b/66b and 8b/10b encoding8b/10b modes are JESD204B compatibleOptional digital down-converters (DDC):4x, 8x, 16x and 32x complex decimationFour independent 32-Bit NCOs per DDCPeak RF Input Power: +26.25dBm (+ 27.5dBFS, 560x fullscale power)Programmable FIR filter for equalizationPower consumption: 4WPower supplies: 1.1V, 1.9VADC core:12-bit resolutionUp to 10.4GSPS in single-channel modeUp to 5.2GSPS in dual-channel modeSingle Ended 50Ω Inputs:Analog input range (–3dB): 2 to 6.3GHzFull-scale input power (4.5GHz): - 1.25dBmFlexible VCM: AC coupled with no DC path to GND or supplyPerformance specifications:Noise floor (2.3GHz, –20dBFS,INPUTFS = 1.5dBm):Dual-channel mode: –149dBFS/HzSingle-channel mode: –151.5dBFS/HzENOB (dual channel, FIN = 2.3GHz): 8.5 BitsNoiseless aperture delay (tAD) adjustment:Precise sampling control: 19fs StepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingJESD204C serial data interface:Maximum lane rate: 17.16GbpsSupport for 64b/66b and 8b/10b encoding8b/10b modes are JESD204B compatibleOptional digital down-converters (DDC):4x, 8x, 16x and 32x complex decimationFour independent 32-Bit NCOs per DDCPeak RF Input Power: +26.25dBm (+ 27.5dBFS, 560x fullscale power)Programmable FIR filter for equalizationPower consumption: 4WPower supplies: 1.1V, 1.9V

Description

The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3dB input frequency range of 2 to 6.3GHz enables direct RF sampling of S-band and C-band for frequency agile systems. The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization. The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3dB input frequency range of 2 to 6.3GHz enables direct RF sampling of S-band and C-band for frequency agile systems. The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.