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SOT-23 (DBV)
Integrated Circuits (ICs)

TPS3840DL47DBVRQ1

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Texas Instruments

AUTOMOTIVE HIGH-INPUT VOLTAGE SUPERVISOR WITH MANUAL RESET AND PROGRAMMABLE-RESET TIME DELAY

SOT-23 (DBV)
Integrated Circuits (ICs)

TPS3840DL47DBVRQ1

Active
Texas Instruments

AUTOMOTIVE HIGH-INPUT VOLTAGE SUPERVISOR WITH MANUAL RESET AND PROGRAMMABLE-RESET TIME DELAY

Technical Specifications

Parameters and characteristics for this part

SpecificationTPS3840DL47DBVRQ1
GradeAutomotive
Mounting TypeSurface Mount
Number of Voltages Monitored1
Operating Temperature [Max]125 ¯C
Operating Temperature [Min]-40 °C
OutputOpen Drain or Open Collector
Package / CaseSC-74A, SOT-753
QualificationAEC-Q100
ResetActive Low
Reset Timeout619 ms
Supplier Device PackageSOT-23-5
TypeSimple Reset/Power-On Reset
Voltage - Threshold4.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.66
10$ 1.05
25$ 0.89
100$ 0.71
250$ 0.62
500$ 0.56
1000$ 0.52
Digi-Reel® 1$ 1.66
10$ 1.05
25$ 0.89
100$ 0.71
250$ 0.62
500$ 0.56
1000$ 0.52
Tape & Reel (TR) 3000$ 0.46
6000$ 0.43
9000$ 0.42
15000$ 0.40
21000$ 0.39
Texas InstrumentsLARGE T&R 1$ 0.76
100$ 0.58
250$ 0.43
1000$ 0.31

Description

General part information

TPS3840-Q1 Series

Wide Vin allows monitoring 9V rails or batteries without external components and 24V rails with external resistors. Nano-Iq extends battery life for low power applications and minimizes current consumption when using external resistors. Fast start-up delay allows the detection of a voltage fault before the rest of the system powers up providing maximum safety in hazardous start-up fault conditions. Low Power-on-Reset (VPOR) prevents false resets, premature enable or turn-on of next device, and proper transistor control during power-up and power-down.

Reset output signal is asserted when the voltage at VDDdrops below the negative voltage threshold (VIT-) or when manual reset (MR) is pulled to a low logic (VMR_L). Reset signal is cleared when VDDrise above VIT-plus hysteresis (VIT+) and manual reset is floating or above VMR_Hand the reset time delay (tD) expires. Reset time delay can be programmed by connecting a capacitor between CT pin and ground. For a fast reset CT pin can be left floating.

Additional features: Built-in glitch immunity protection forMRand VDD, built-in hysteresis, low open-drain output leakage current (ILKG(OD)).