Specification	CLVC1G175MDCKREP

Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	10 µA
Function	Reset
Input Capacitance	3 pF
Max Propagation Delay @ V, Max CL	5 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Non-Inverted
Package / Case	6-TSSOP, SC-88, SOT-363
Supplier Device Package	SC-70-6
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC1G175-EP Series

Enhanced Product Single D-Type Flip-Flop With Asynchronous Clear

Part	Mounting Type	Package / Case	Input Capacitance	Max Propagation Delay @ V, Max CL	Number of Elements	Function	Current - Quiescent (Iq)	Output Type	Supplier Device Package	Current - Output High, Low [y]	Current - Output High, Low [x]	Type	Trigger Type	Number of Bits per Element	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments CLVC1G175MDCKREP	Surface Mount	6-TSSOP SC-88 SOT-363	3 pF	5 ns	1	Reset	10 µA	Non-Inverted	SC-70-6	32 mA	32 mA	D-Type	Positive Edge	1	5.5 V	1.65 V	125 °C	-55 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 2.83
		10	$ 1.83
		25	$ 1.57
		100	$ 1.28
		250	$ 1.13
		500	$ 1.05
		1000	$ 0.97
	Digi-Reel®	1	$ 2.83
		10	$ 1.83
		25	$ 1.57
		100	$ 1.28
		250	$ 1.13
		500	$ 1.05
		1000	$ 0.97
	Tape & Reel (TR)	3000	$ 0.88
		6000	$ 0.84
		9000	$ 0.82
Texas Instruments	LARGE T&R	1	$ 1.65
		100	$ 1.36
		250	$ 0.98
		1000	$ 0.74

Description

General part information

SN74LVC1G175-EP Series

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC1G175 has an asynchronous clear (CLR) input. WhenCLRis high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. WhenCLRis low, Q is forced into the low state, regardless of the clock edge or data on D.

This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Documents

Technical documentation and resources

CLVC1G175MDCKREP

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CLVC1G175MDCKREP

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Technical Specifications

SN74LVC1G175-EP Series

Pricing

Description

SN74LVC1G175-EP Series

Documents

Design Summary for WCSP Little Logic (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

LVC Characterization Information

Input and Output Characteristics of Digital Integrated Circuits

How to Select Little Logic (Rev. A)

Little Logic Guide 2018 (Rev. G)

TI IBIS File Creation, Validation, and Distribution Processes

Implications of Slow or Floating CMOS Inputs (Rev. E)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Low-Voltage Logic (LVC) Designer's Guide

Live Insertion

SN74LVC1G175-EP datasheet (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

LOGIC Pocket Data Book (Rev. B)

Selecting the Right Level Translation Solution (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

CMOS Power Consumption and CPD Calculation (Rev. B)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Texas Instruments Little Logic Application Report

Standard Linear & Logic for PCs, Servers & Motherboards

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Signal Switch Data Book (Rev. A)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Power-Up Behavior of Clocked Devices (Rev. B)

Logic Guide (Rev. AB)

SN74LVC1G175-EP Series