Zenode.ai Logo
Beta
SN74LVC1G175-EP

SN74LVC1G175-EP Series

Enhanced Product Single D-Type Flip-Flop With Asynchronous Clear

Manufacturer: Texas Instruments

Catalog

Enhanced Product Single D-Type Flip-Flop With Asynchronous Clear

Key Features

Supports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.3 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial Power-Down-Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)APPLICATIONSControlled BaselineOne Assembly/Test SiteOne Fabrication SiteAvailable in Military (–55°C/125°C)Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Additional temperature ranges available - contact factorySupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.3 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial Power-Down-Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)APPLICATIONSControlled BaselineOne Assembly/Test SiteOne Fabrication SiteAvailable in Military (–55°C/125°C)Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Additional temperature ranges available - contact factory

Description

AI
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G175 has an asynchronous clear (CLR) input. WhenCLRis high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. WhenCLRis low, Q is forced into the low state, regardless of the clock edge or data on D. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G175 has an asynchronous clear (CLR) input. WhenCLRis high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. WhenCLRis low, Q is forced into the low state, regardless of the clock edge or data on D. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.