
SN74ALVTH16374VR
Obsolete2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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SN74ALVTH16374VR
Obsolete2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVTH16374VR |
|---|---|
| Clock Frequency | 250 MHz |
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 32 mA |
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 8 mA |
| Current - Quiescent (Iq) | 100 µA |
| Function | Standard |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 3.2 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 0.173 in, 4.4 mm |
| Package / Case | 48-TFSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 2.7 V, 3.6 V |
| Voltage - Supply [Min] | 2.3 V, 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| LCSC | Piece | 1 | $ 4.72 | |
| 200 | $ 1.83 | |||
| 500 | $ 1.76 | |||
| 1000 | $ 1.73 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.40 | |
| 100 | $ 1.15 | |||
| 250 | $ 0.83 | |||
| 1000 | $ 0.62 | |||
Description
General part information
SN74ALVTH16374 Series
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
Documents
Technical documentation and resources