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16 LFCSP-VQ
Integrated Circuits (ICs)

ADCMP580BCPZ-R2

Unknown
Analog Devices

IC COMPARATOR 1 W/LATCH 16LFCSP

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16 LFCSP-VQ
Integrated Circuits (ICs)

ADCMP580BCPZ-R2

Unknown
Analog Devices

IC COMPARATOR 1 W/LATCH 16LFCSP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationADCMP580BCPZ-R2
CMRR, PSRR (Typ)75 dB, 60 dB
Current - Input Bias (Max)30 µA
Current - Output (Typ)44 mA
Current - Quiescent (Max) [Max]8 mA
Hysteresis1 mV
Mounting TypeSurface Mount
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeCML, Complementary
Package / Case16-WFQFN Exposed Pad, CSP
Propagation Delay (Max) [Max]0.18 ns
Supplier Device Package16-LFCSP (3x3)
Typewith Latch
Voltage - Input Offset (Max)10 mV
Voltage - Supply, Single/Dual (±) [Max]5.5 V
Voltage - Supply, Single/Dual (±) [Min]-4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

ADCMP580 Series

The ADCMP580/ADCMP581/ADCMP582are ultrafast voltage comparators fabricated on the Analog Devices, Inc. proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers, the ADCMP581 features reduced swing ECL (negative ECL) output drivers, and the ADCMP582 features reduced swing PECL (positive ECL) output drivers.All three comparators offer 180 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps.The ±5 V power supplies enable a wide −2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The inputs have 50 Ω on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input.The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to ground. The NECL output stages are designed to directly drive 400 mV into 50 Ω terminated to −2 V. The PECL output stages are designed to directly drive 400 mV into 50 Ω terminated to VCCO− 2 V. High speed latch and programmable hysteresis are also provided. The differential latch input controls are also 50 Ω terminated to an independent VTT pin to interface to either CML or ECL or to PECL logic.The ADCMP580/ADCMP581/ADCMP582 are available in a 16-lead LFCSP.ApplicationsAutomatic test equipment (ATE)High speed instrumentationPulse spectroscopyMedical imaging and diagnosticsHigh speed line receiversThreshold detectionPeak and zero-crossing detectorsHigh speed trigger circuitryClock and data signal restoration

Documents

Technical documentation and resources