Specification	SN74ABT373N

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Delay Time - Propagation	4.6 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Through Hole
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-DIP
Package / Case	7.62 mm
Package / Case	0.3 in
Supplier Device Package	20-PDIP
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ABT373 Series

Octal Transparent D-Type Latches With 3-State Outputs

Part	Circuit [custom]	Circuit [custom]	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Independent Circuits	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Package / Case	Package / Case	Package / Case	Delay Time - Propagation	Output Type	Package / Case [y]	Package / Case [x]	Package / Case [y]
Texas Instruments SN74ABT373DB
Texas Instruments SN74ABT373N	8	8	Through Hole	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-PDIP	20-DIP	7.62 mm	0.3 in	4.6 ns	Tri-State
Texas Instruments SN74ABT373DBRG4	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-SSOP	20-SSOP			4.6 ns	Tri-State
Texas Instruments SN74ABT373PWE4	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-TSSOP	20-TSSOP			4.6 ns	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74ABT373NSR	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-SO	20-SOIC	5.3 mm	0.209 "	4.6 ns	Tri-State
Texas Instruments SN74ABT373DWR	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-SOIC	20-SOIC			4.6 ns	Tri-State	0.295 in		7.5 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Arrow	N/A	20	$ 0.74
Digikey	Tube	1	$ 0.68
		20	$ 0.61
		40	$ 0.58
		100	$ 0.47
		260	$ 0.44
		500	$ 0.39
		1000	$ 0.36
Texas Instruments	TUBE	1	$ 1.56
		100	$ 1.20
		250	$ 0.88
		1000	$ 0.63

Description

General part information

SN74ABT373 Series

The eight latches of the 'ABT373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Documents

Technical documentation and resources

SN74ABT373N

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SN74ABT373N

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Technical Specifications

SN74ABT373 Series

Pricing

Description

SN74ABT373 Series

Documents

Power-Up Behavior of Clocked Devices (Rev. B)

Logic Guide (Rev. AB)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. D)

Input and Output Characteristics of Digital Integrated Circuits

Advanced Bus Interface Logic Selection Guide

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Quad Flatpack No-Lead Logic Packages (Rev. D)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Live Insertion

Designing With Logic (Rev. C)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

Selecting the Right Level Translation Solution (Rev. A)

LOGIC Pocket Data Book (Rev. B)

Understanding Advanced Bus-Interface Products Design Guide

TI IBIS File Creation, Validation, and Distribution Processes

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN74ABT373 Series