SN74ABT373 Series

Octal Transparent D-Type Latches With 3-State Outputs

Catalog

Octal Transparent D-Type Latches With 3-State Outputs

Part	Circuit [custom]	Circuit [custom]	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Independent Circuits	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Package / Case	Package / Case	Package / Case	Delay Time - Propagation	Output Type	Package / Case [y]	Package / Case [x]	Package / Case [y]
Texas Instruments SN74ABT373DB
Texas Instruments SN74ABT373N	8	8	Through Hole	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-PDIP	20-DIP	7.62 mm	0.3 in	4.6 ns	Tri-State
Texas Instruments SN74ABT373DBRG4	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-SSOP	20-SSOP			4.6 ns	Tri-State
Texas Instruments SN74ABT373PWE4	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-TSSOP	20-TSSOP			4.6 ns	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74ABT373NSR	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-SO	20-SOIC	5.3 mm	0.209 "	4.6 ns	Tri-State
Texas Instruments SN74ABT373DWR	8	8	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	1	4.5 V	5.5 V	64 mA	32 mA	20-SOIC	20-SOIC			4.6 ns	Tri-State	0.295 in		7.5 mm

Catalog

Octal Transparent D-Type Latches With 3-State Outputs

Key Features

• State-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (N) and Ceramic (J) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.State-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (N) and Ceramic (J) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.

Description

The eight latches of the 'ABT373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT373 is characterized for operation from -40°C to 85°C. The eight latches of the 'ABT373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT373 is characterized for operation from -40°C to 85°C.