SN74ALS534ADWR
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN SOIC T/R
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SN74ALS534ADWR
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN SOIC T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALS534ADWR |
|---|---|
| Clock Frequency | 35 MHz |
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 2.6 mA |
| Current - Quiescent (Iq) | 19 mA |
| Function | Standard |
| Max Propagation Delay @ V, Max CL | 16 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Tri-State, Inverted |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.04 | |
| 10 | $ 2.73 | |||
| 25 | $ 2.58 | |||
| 100 | $ 2.23 | |||
| 250 | $ 2.12 | |||
| 500 | $ 2.02 | |||
| Digi-Reel® | 1 | $ 3.04 | ||
| 10 | $ 2.73 | |||
| 25 | $ 2.58 | |||
| 100 | $ 2.23 | |||
| 250 | $ 2.12 | |||
| 500 | $ 2.02 | |||
| Tape & Reel (TR) | 2000 | $ 2.10 | ||
| 4000 | $ 2.02 | |||
| Texas Instruments | LARGE T&R | 1 | $ 3.75 | |
| 100 | $ 3.29 | |||
| 250 | $ 2.30 | |||
| 1000 | $ 1.86 | |||
Description
General part information
SN74ALS534A Series
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q\ outputs are set to the complement of the logic states set up at the data (D) inputs. The 'ALS534A and SN74AS534 have inverted outputs, but otherwise are functionally equivalent to the 'ALS374A and SN74AS374.
A buffered output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Documents
Technical documentation and resources
