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Texas Instruments-TLC5510AINSR Analog to Digital Converters - ADCs 1-Channel Single ADC Semiflash 20Msps 8-bit Parallel 24-Pin SOP T/R
Integrated Circuits (ICs)

SN74ABT646ADGVR

Obsolete
Texas Instruments

BUS XCVR SINGLE 8-CH 3-ST 24-PIN TVSOP T/R

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Texas Instruments-TLC5510AINSR Analog to Digital Converters - ADCs 1-Channel Single ADC Semiflash 20Msps 8-bit Parallel 24-Pin SOP T/R
Integrated Circuits (ICs)

SN74ABT646ADGVR

Obsolete
Texas Instruments

BUS XCVR SINGLE 8-CH 3-ST 24-PIN TVSOP T/R

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ABT646ADGVR
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case24-TFSOP
Package / Case [y]4.4 mm
Package / Case [y]0.173 in
Supplier Device Package24-TVSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

SN74ABT646A Series

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´ABT646.

Output-enable () and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data whenis low. In the isolation mode (high), A data may be stored in one register and/or B data may be stored in the other register.

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Technical documentation and resources

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