SCANSTA101SM/NOPB
ActiveLOW VOLTAGE IEEE 1149.1 SYSTEM TEST ACCESS (STA) MASTER
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SCANSTA101SM/NOPB
ActiveLOW VOLTAGE IEEE 1149.1 SYSTEM TEST ACCESS (STA) MASTER
Technical Specifications
Parameters and characteristics for this part
| Specification | SCANSTA101SM/NOPB |
|---|---|
| Applications | Testing Equipment |
| Interface | IEEE 1149.1 |
| Mounting Type | Surface Mount |
| Package / Case | 49-LFBGA |
| Supplier Device Package | 49-NFBGA (7x7) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 22.05 | |
| 10 | $ 17.66 | |||
| 25 | $ 16.56 | |||
| 100 | $ 15.35 | |||
| 416 | $ 14.51 | |||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 17.44 | |
| 100 | $ 15.23 | |||
| 250 | $ 11.74 | |||
| 1000 | $ 10.50 | |||
Description
General part information
SCANSTA101 Series
The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan test system. It is suitable for use in embedded IEEE 1149.1 applications and as a component in a stand-alone boundary scan tester.
The SCANSTA101 is an enhanced version of, and a replacement for, the SCANPSC100. The SCANSTA101 supports the IEEE 1149.1 Test Access Port (TAP) standard and the IEEE 1532 standard for in-system configuration of programmable devices.
The SCANSTA101 improves test vector throughput and reduces software overhead in the system processor. The SCANSTA101 presents a simple, register-based interface to the system processor. Texas Instruments provides C-language source code which can be included in the embedded system software. The combination of the SCANSTA101 and its support software comprises a simple API for boundary scan operations.