
AD9608BCPZRL7-125
Active2-CHANNEL DUAL ADC PIPELINED 125MSPS 10-BIT PARALLEL/LVDS 64-PIN LFCSP EP T/R
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AD9608BCPZRL7-125
Active2-CHANNEL DUAL ADC PIPELINED 125MSPS 10-BIT PARALLEL/LVDS 64-PIN LFCSP EP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | AD9608BCPZRL7-125 |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Parallel |
| Features | Simultaneous Sampling |
| Input Type | Single Ended, Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Bits [custom] | 10 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 64-VFQFN Exposed Pad, CSP |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 125 M |
| Supplier Device Package | 64-LFCSP-VQ (9x9) |
| Voltage - Supply, Analog [Max] | 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V |
| Voltage - Supply, Digital [Max] | 1.9 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 750 | $ 31.14 | |
Description
General part information
AD9608 Series
The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus.The AD9608 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).PRODUCT HIGHLIGHTSOperates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families.The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.Includes a standard serial port interface that supports various product features and functions, such as data output format-ting, internal clock divider, power-down, DCO/data timing, and offset adjustments.Packaged in a 64-lead, RoHS-compliant LFCSP that is pin compatible with theAD9650,AD9269andAD926816-bit ADC’s, theAD9258andAD964814-bit ADC, theAD9628andAD923112-bit ADC’s, and theAD920410-bit ADC’s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.APPLICATIONSCommunicationsDiversity radio systemsI/Q demodulation systemsBroadband data applicationsBattery-powered instrumentsHand held scope metersPortable medical imagingUltrasound
Documents
Technical documentation and resources