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Integrated Circuits (ICs)

SN74ABT8996DW

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Texas Instruments

10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1194.1 (JTAG) TAP TRANSCEIVERS

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24-pin (DW) package image
Integrated Circuits (ICs)

SN74ABT8996DW

Active
Texas Instruments

10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1194.1 (JTAG) TAP TRANSCEIVERS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ABT8996DW
Logic TypeAddressable Scan Ports
Mounting TypeSurface Mount
Number of Bits [custom]10
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
Supplier Device Package160-NFBGA (9x13)
Supply Voltage [Max]5.5 V
Supply Voltage [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 75$ 15.32
Texas InstrumentsTUBE 1$ 15.65
100$ 13.67
250$ 10.54
1000$ 9.43

Description

General part information

SN74ABT8996 Series

The 'ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TITM) SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETMdevices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Standard 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.

Most operations of the ASP are synchronous to the primary test clock (PTCK) input. This PTCK signal always is buffered directly onto the secondary test clock (STCK) output.