Zenode.ai Logo
Beta

Technical Specifications

Parameters and characteristics for this part

SpecificationFPC402RHUT
InterfaceI2C
Mounting TypeSurface Mount
Package / Case56-WFQFN Exposed Pad
Supplier Device Package56-WQFN (5x11)
Voltage - Supply [Max]3.3 V
Voltage - Supply [Min]1.8 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 10.80
10$ 7.54
25$ 6.70
100$ 5.76
Digi-Reel® 1$ 10.80
10$ 7.54
25$ 6.70
100$ 5.76
Tape & Reel (TR) 250$ 5.31
500$ 5.03
750$ 4.89
1250$ 4.75
Texas InstrumentsSMALL T&R 1$ 7.00
100$ 5.70
250$ 4.48
1000$ 3.80

Description

General part information

FPC402 Series

The FPC402 quad port controller serves as a low-speed signal aggregator for common port types such as SFP, QSFP, Mini-SAS HD, and others. The FPC402 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC402s can be used in high-port-count applications with one common control interface to the host. The FPC402 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the low-speed signals in the ports cuts system BOM costs by enabling the use of smaller IO count control devices (FPGAs, CPLDs, and MCUs) and by reducing routing layer congestion.

The FPC402 quad port controller serves as a low-speed signal aggregator for common port types such as SFP, QSFP, Mini-SAS HD, and others. The FPC402 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC402s can be used in high-port-count applications with one common control interface to the host. The FPC402 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the low-speed signals in the ports cuts system BOM costs by enabling the use of smaller IO count control devices (FPGAs, CPLDs, and MCUs) and by reducing routing layer congestion.