STM32L4Q5CGU6P
ActiveULTRA-LOW-POWER WITH FPU ARM CORTEX-M4 MCU 120 MHZ WITH 1024 KBYTES OF FLASH MEMORY, USB OTG, DFSDM, CHROM-ART, AES, PKA
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STM32L4Q5CGU6P
ActiveULTRA-LOW-POWER WITH FPU ARM CORTEX-M4 MCU 120 MHZ WITH 1024 KBYTES OF FLASH MEMORY, USB OTG, DFSDM, CHROM-ART, AES, PKA
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32L4Q5CGU6P |
|---|---|
| Connectivity | IrDA, EBI/EMI, CANbus, MMC/SD, I2C, SAI, LINbus, USB OTG, SPI, UART/USART |
| Core Processor | ARM® Cortex®-M4 |
| Core Size | 32-Bit |
| Data Converters | D/A 2x12b, A/D 16x12b |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Oscillator Type | Internal |
| Package / Case | 48-UFQFN Exposed Pad |
| Peripherals | POR, (External SMPS Required), LCD, WDT, DMA, Brown-out Detect/Reset, PWM |
| Program Memory Size | 1 MB |
| Program Memory Type | FLASH |
| RAM Size | 320 K |
| Speed | 120 MHz |
| Supplier Device Package | 48-UFQFPN (7x7) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
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Description
General part information
STM32L4Q5CG Series
STM32L4Q5xx designates a family of ultra-low-power microcontroller devices (part of STM32L4+ Series) based on the high-performance Arm®Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 120 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex-M4 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application’s security.
These devices embed high-speed memories (1 Mbyte of Flash memory and 320 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), two OCTOSPI Flash memory interfaces (for devices with packages of 100 pins or more) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources
