Zenode.ai Logo
Beta
16-DIP SOT38-1
Integrated Circuits (ICs)

CD4015BEG4

Unknown
Texas Instruments

IC DUAL STATIC SHFT REG 16-DIP

Deep-Dive with AI

Search across all available documentation for this part.

16-DIP SOT38-1
Integrated Circuits (ICs)

CD4015BEG4

Unknown
Texas Instruments

IC DUAL STATIC SHFT REG 16-DIP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4015BEG4
FunctionSerial to Parallel
Logic TypeShift Register
Mounting TypeThrough Hole
Number of Bits per Element4
Number of Elements2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypePush-Pull
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1700$ 0.25

Description

General part information

CD4015B Series

CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015B package, or to more than 8 stages using additional CD4015B’s is possible.

The CD4015B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015B package, or to more than 8 stages using additional CD4015B’s is possible.

Documents

Technical documentation and resources

No documents available