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TSSOP (PW)
Integrated Circuits (ICs)

SN74AHC139PWR

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Texas Instruments

DUAL 2-LINE TO 4-LINE DEMULTIPLEXER AND DECODER

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TSSOP (PW)
Integrated Circuits (ICs)

SN74AHC139PWR

Active
Texas Instruments

DUAL 2-LINE TO 4-LINE DEMULTIPLEXER AND DECODER

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AHC139PWR
Circuit1 x 2:4
Current - Output High, Low [custom]8 mA
Current - Output High, Low [custom]8 mA
Independent Circuits2
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
TypeDecoder/Demultiplexer
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.52
10$ 0.42
25$ 0.38
100$ 0.28
250$ 0.26
500$ 0.21
1000$ 0.16
Digi-Reel® 1$ 0.52
10$ 0.42
25$ 0.38
100$ 0.28
250$ 0.26
500$ 0.21
1000$ 0.16
Tape & Reel (TR) 2000$ 0.11
Texas InstrumentsLARGE T&R 1$ 0.24
100$ 0.16
250$ 0.13
1000$ 0.08

Description

General part information

SN74AHC139 Series

The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.