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16-DIP SOT38-1
Integrated Circuits (ICs)

SN74AHC139N

Active
Texas Instruments

DUAL 2-LINE TO 4-LINE DEMULTIPLEXER AND DECODER

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16-DIP SOT38-1
Integrated Circuits (ICs)

SN74AHC139N

Active
Texas Instruments

DUAL 2-LINE TO 4-LINE DEMULTIPLEXER AND DECODER

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AHC139N
Circuit1 x 2:4
Current - Output High, Low [custom]8 mA
Current - Output High, Low [custom]8 mA
Independent Circuits2
Mounting TypeThrough Hole
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
TypeDecoder/Demultiplexer
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.46
10$ 0.40
25$ 0.38
100$ 0.31
250$ 0.29
500$ 0.24
1000$ 0.21
Texas InstrumentsTUBE 1$ 0.64
100$ 0.44
250$ 0.34
1000$ 0.22

Description

General part information

SN74AHC139 Series

The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.