Specification	SN74LV74ARGYR

Clock Frequency	140 MHz
Current - Output High, Low [custom]	12 mA
Current - Output High, Low [custom]	12 mA
Current - Quiescent (Iq)	20 çA
Function	Reset, Set(Preset)
Input Capacitance	2 pF
Max Propagation Delay @ V, Max CL	9.3 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-VFQFN Exposed Pad
Supplier Device Package	14-VQFN (3.5x3.5)
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	2 V

SN74LV74A-Q1 Series

Automotive Catalog Dual Positive-Edge-Triggered D-Type Flip-Flop

Part	Max Propagation Delay @ V, Max CL	Input Capacitance	Current - Quiescent (Iq)	Operating Temperature [Min]	Operating Temperature [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Clock Frequency	Function	Package / Case [x]	Package / Case [y]	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Type	Mounting Type	Trigger Type	Number of Elements	Output Type	Number of Bits per Element	Supplier Device Package	Package / Case [custom]	Package / Case [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Grade	Qualification
Texas Instruments SN74LV74ADR	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)	0.154 in	3.9 mm	14-SOIC	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1
Texas Instruments SN74LV74AD	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)	0.154 in	3.9 mm	14-SOIC	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1
Texas Instruments SN74LV74APWRE4	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)			14-TSSOP	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-TSSOP	0.173 "	4.4 mm
Texas Instruments SN74LV74APWT	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)			14-TSSOP	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-TSSOP	0.173 "	4.4 mm
Texas Instruments V62/06605-01XE		2 pF	20 çA			12 mA	12 mA	140 MHz	Reset Set(Preset)			14-TSSOP	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-TSSOP	0.173 "	4.4 mm	125 °C	-55 °C
Texas Instruments SN74LV74ARGYR	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)			14-VFQFN Exposed Pad	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-VQFN (3.5x3.5)
Texas Instruments SN74LV74AQDRQ1	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)	0.154 in	3.9 mm	14-SOIC	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1						Automotive	AEC-Q100
Texas Instruments SN74LV74AQPWRG4Q1	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)			14-TSSOP	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-TSSOP	0.173 "	4.4 mm			Automotive	AEC-Q100
Texas Instruments SN74LV74APW	9.3 ns	2 pF	20 çA	-40 °C	125 °C	12 mA	12 mA	140 MHz	Reset Set(Preset)			14-TSSOP	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-TSSOP	0.173 "	4.4 mm
Texas Instruments SN74LV74AMPWREP		2 pF	20 çA			12 mA	12 mA	140 MHz	Reset Set(Preset)			14-TSSOP	5.5 V	2 V	D-Type	Surface Mount	Positive Edge	2	Complementary	1	14-TSSOP	0.173 "	4.4 mm	125 °C	-55 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.65
		10	$ 0.55
		25	$ 0.52
		100	$ 0.41
		250	$ 0.38
		500	$ 0.32
		1000	$ 0.25
	Digi-Reel®	1	$ 0.65
		10	$ 0.55
		25	$ 0.52
		100	$ 0.41
		250	$ 0.38
		500	$ 0.32
		1000	$ 0.25
	Tape & Reel (TR)	3000	$ 0.09
Texas Instruments	LARGE T&R	1	$ 0.20
		100	$ 0.14
		250	$ 0.10
		1000	$ 0.07

Description

General part information

SN74LV74A-Q1 Series

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCCoperation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.