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Texas Instruments-DS32ELX0421SQE/NOPB LVDS LVDS Serializer 3125Mbps 48-Pin WQFN EP T/R
Integrated Circuits (ICs)

LMK03001CISQX/NOPB

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Texas Instruments

1470 TO 1570-MHZ, 800-FS RMS JITTER, PRECISION CLOCK CONDITIONER WITH INTEGRATED VCO

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Texas Instruments-DS32ELX0421SQE/NOPB LVDS LVDS Serializer 3125Mbps 48-Pin WQFN EP T/R
Integrated Circuits (ICs)

LMK03001CISQX/NOPB

Active
Texas Instruments

1470 TO 1570-MHZ, 800-FS RMS JITTER, PRECISION CLOCK CONDITIONER WITH INTEGRATED VCO

Technical Specifications

Parameters and characteristics for this part

SpecificationLMK03001CISQX/NOPB
Differential - Input:Output [custom]True
Differential - Input:Output [custom]True
Divider/MultiplierYes/No
Frequency - Max [Max]1.57 GHz
InputLVDS, LVCMOS, LVPECL
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputLVPECL, LVDS
Package / Case48-WFQFN Exposed Pad
PLLFalse
Ratio - Input:Output1:8
Supplier Device Package48-WQFN (7x7)
TypeClock Conditioner
Voltage - Supply [Max]3.45 V
Voltage - Supply [Min]3.15 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2500$ 19.18
Texas InstrumentsLARGE T&R 1$ 25.02
100$ 21.86
250$ 16.85
1000$ 15.07

Description

General part information

LMK03001 Series

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.