CD74HC4015M
ActiveHIGH SPEED CMOS LOGIC DUAL 4-STAGE STATIC SHIFT REGISTERS
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CD74HC4015M
ActiveHIGH SPEED CMOS LOGIC DUAL 4-STAGE STATIC SHIFT REGISTERS
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC4015M |
|---|---|
| Function | Serial to Parallel |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 4 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Push-Pull |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 1.53 | |
| 10 | $ 1.37 | |||
| 40 | $ 1.29 | |||
| 120 | $ 1.10 | |||
| 280 | $ 1.03 | |||
| 520 | $ 0.90 | |||
| 1000 | $ 0.75 | |||
| 2520 | $ 0.70 | |||
| 5000 | $ 0.67 | |||
| Texas Instruments | TUBE | 1 | $ 1.32 | |
| 100 | $ 1.09 | |||
| 250 | $ 0.78 | |||
| 1000 | $ 0.59 | |||
Description
General part information
CD74HC4015 Series
The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.
The device can drive up to 10 low power Schottky equivalent loads. The ’HC4015 is an enhanced version of equivalent CMOS types.
The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.
Documents
Technical documentation and resources
