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16 SOIC
Integrated Circuits (ICs)

CD4018BM96

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Texas Instruments

CMOS PRESETTABLE DIVIDE-BY-N COUNTER

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16 SOIC
Integrated Circuits (ICs)

CD4018BM96

Active
Texas Instruments

CMOS PRESETTABLE DIVIDE-BY-N COUNTER

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4018BM96
Count Rate8.5 MHz
Logic TypeDivide-by-N
Mounting TypeSurface Mount
Number of Bits per Element5
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
ResetAsynchronous
Supplier Device Package16-SOIC
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.47
10$ 0.40
25$ 0.37
100$ 0.30
250$ 0.28
500$ 0.24
1000$ 0.18
Digi-Reel® 1$ 0.47
10$ 0.40
25$ 0.37
100$ 0.30
250$ 0.28
500$ 0.24
1000$ 0.18
Tape & Reel (TR) 2500$ 0.17
5000$ 0.16
12500$ 0.14
25000$ 0.14
62500$ 0.13
Texas InstrumentsLARGE T&R 1$ 0.39
100$ 0.26
250$ 0.20
1000$ 0.13

Description

General part information

CD4018B-MIL Series

CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.

The CD4018B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.

Documents

Technical documentation and resources