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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4018BNSR |
|---|---|
| Count Rate | 8.5 MHz |
| Logic Type | Divide-by-N |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 5 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 0.209 " |
| Package / Case | 16-SOIC |
| Package / Case | 5.3 mm |
| Reset | Asynchronous |
| Supplier Device Package | 16-SO |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
CD4018B-MIL Series
CMOS Presettable Divide-By-N Counter
| Part | Voltage - Supply [Max] | Voltage - Supply [Min] | Number of Bits per Element | Logic Type | Operating Temperature [Min] | Operating Temperature [Max] | Reset | Count Rate | Supplier Device Package | Mounting Type | Trigger Type | Timing | Package / Case | Package / Case | Package / Case | Number of Elements | Package / Case [x] | Package / Case [y] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-SO | Surface Mount | Positive Edge | Synchronous | 0.209 " | 16-SOIC | 5.3 mm | 1 | ||
 Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-TSSOP | Surface Mount | Positive Edge | Synchronous | 16-TSSOP | 1 | 0.173 in | 4.4 mm | ||
 Texas Instruments | ||||||||||||||||||
Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-TSSOP | Surface Mount | Positive Edge | Synchronous | 16-TSSOP | 1 | 0.173 in | 4.4 mm | ||
 Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-SOIC | Surface Mount | Positive Edge | Synchronous | 16-SOIC | 1 | 0.154 in | 3.9 mm | ||
 Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-PDIP | Through Hole | Positive Edge | Synchronous | 0.3 in | 16-DIP | 7.62 mm | 1 | ||
 Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-SOIC | Surface Mount | Positive Edge | Synchronous | 16-SOIC | 1 | 0.154 in | 3.9 mm | ||
Texas Instruments | 18 V | 3 V | 5 | Divide-by-N | -55 °C | 125 °C | Asynchronous | 8.5 MHz | 16-SOIC | Surface Mount | Positive Edge | Synchronous | 16-SOIC | 1 | 0.154 in | 3.9 mm |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.58 | |
| 10 | $ 0.51 | |||
| 25 | $ 0.48 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.37 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.25 | |||
| Digi-Reel® | 1 | $ 0.58 | ||
| 10 | $ 0.51 | |||
| 25 | $ 0.48 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.37 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.25 | |||
| Tape & Reel (TR) | 2000 | $ 0.19 | ||
| Texas Instruments | LARGE T&R | 1 | $ 0.51 | |
| 100 | $ 0.34 | |||
| 250 | $ 0.27 | |||
| 1000 | $ 0.18 | |||
Description
General part information
CD4018B-MIL Series
CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.
The CD4018B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.
Documents
Technical documentation and resources