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CAHCT164QWBQARQ1

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Texas Instruments

AUTOMOTIVE, 4.5-V TO 5.5-V 8-BIT, PARALLEL-OUT SERIAL SHIFT REGISTERS

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14-pin (BQA) package image
Uncategorized

CAHCT164QWBQARQ1

Active
Texas Instruments

AUTOMOTIVE, 4.5-V TO 5.5-V 8-BIT, PARALLEL-OUT SERIAL SHIFT REGISTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationCAHCT164QWBQARQ1
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Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsLARGE T&R 1$ 0.34
100$ 0.23
250$ 0.18
1000$ 0.12

Description

General part information

SN74AHCT164-Q1 Series

The SN74AHCT164-Q1 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The SN74AHCT164-Q1 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.