SN74ALVCH16524DGGR
ObsoleteBUS XCVR SINGLE 18-CH 3-ST 56-PIN TSSOP T/R
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SN74ALVCH16524DGGR
ObsoleteBUS XCVR SINGLE 18-CH 3-ST 56-PIN TSSOP T/R
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH16524DGGR |
|---|---|
| Current - Output High, Low | 24 mA |
| Mounting Type | Surface Mount |
| Number of Circuits | 18 Bit |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 6.1 mm |
| Package / Case | 0.24 in |
| Package / Case | 56-TFSOP |
| Supplier Device Package | 56-TSSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74ALVCH16524 Series
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.
Documents
Technical documentation and resources