SN74ALVCH16524 Series
18-Bit Registered Bus Transceiver With 3-State Outputs
Manufacturer: Texas Instruments
Catalog
18-Bit Registered Bus Transceiver With 3-State Outputs
Key Features
• Member of the Texas Instruments Widebus™ FamilyUBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable ModeOperates From 1.65-V to 3.6-VMax tpdof 3.2 ns at 3.3-V±24-mA Output Drive at 3.3-VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Performance Tested Per JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus, UBT are trademarks of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyUBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable ModeOperates From 1.65-V to 3.6-VMax tpdof 3.2 ns at 3.3-V±24-mA Output Drive at 3.3-VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Performance Tested Per JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus, UBT are trademarks of Texas Instruments.
Description
AI
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
