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HCF4021YM013TR
Integrated Circuits (ICs)

HCF4021YM013TR

Active
STMicroelectronics

SHIFT REGISTER, HCF4021, PARALLEL TO SERIAL, SERIAL TO SERIAL, 1 ELEMENT, 8 BIT, SOIC, 16 PINS

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HCF4021YM013TR
Integrated Circuits (ICs)

HCF4021YM013TR

Active
STMicroelectronics

SHIFT REGISTER, HCF4021, PARALLEL TO SERIAL, SERIAL TO SERIAL, 1 ELEMENT, 8 BIT, SOIC, 16 PINS

Technical Specifications

Parameters and characteristics for this part

SpecificationHCF4021YM013TR
FunctionParallel or Serial to Serial
GradeAutomotive
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element [custom]8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 C
Output TypePush-Pull
Package / Case16-SOIC
Package / Case0.154 in, 3.9 mm
QualificationAEC-Q100
Supplier Device Package16-SO
Voltage - Supply [Max]20 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyN/A 3645$ 1.07
MouserN/A 1$ 0.92
10$ 0.70
25$ 0.65
100$ 0.59
250$ 0.56
500$ 0.55
1000$ 0.50
2500$ 0.47
NewarkEach (Supplied on Cut Tape) 1$ 0.92
10$ 0.71
25$ 0.67
50$ 0.62
100$ 0.58

Description

General part information

HCF4021 Series

The HCF4021 is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in PDIP-16 and SO-16 packages.

This device is an 8-stage parallel or serial-input/serial-output register having common clock and parallel/serial control inputs, a single serial data input, and individual parallel "jam" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8. "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous.

In this device, entry is controlled by the parallel/serial control input. When the parallel/serial control input is low, data are serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the parallel/serial control input is high, data are jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. The clock input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.