The HMC679LC3C is a T Flip-Flop w/Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-two function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications.The HMC679LC3C also features an output level control pin, VR, which allows for loss compensation or for signal level optimization. All input signals to the HMC679LC3C are terminated with 50Ω to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50Ω to a non-ground DC voltage. The HMC679LC3C operates from a single -3.3V dc supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONSSerial Data Transmission up to 26 GbpsHigh Speed Frequency Divider (up to 26 GHz)Broadband Test & MeasurementRF ATE Applications