MIC68200-3.3YML-TR
Active2A PEAK FPGA/CPLD LDO WITH POR, RAMP CONTROL, AND SEQUENCING 10 VDFN 3X3X0.9MM T/R ROHS COMPLIANT: YES
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MIC68200-3.3YML-TR
Active2A PEAK FPGA/CPLD LDO WITH POR, RAMP CONTROL, AND SEQUENCING 10 VDFN 3X3X0.9MM T/R ROHS COMPLIANT: YES
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Technical Specifications
Parameters and characteristics for this part
| Specification | MIC68200-3.3YML-TR |
|---|---|
| Control Features | Enable, Power on Reset |
| Current - Output | 1 A |
| Current - Quiescent (Iq) | 15 mA |
| Current - Supply (Max) [Max] | 80 mA |
| Mounting Type | Surface Mount |
| Number of Regulators | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Configuration | Positive |
| Output Type | 1.81 mOhm |
| Package / Case | 10-MLF®, 10-VFDFN Exposed Pad |
| Protection Features | Over Current, Over Temperature |
| Supplier Device Package | 10-MLF® (3x3) |
| Voltage - Input (Max) [Max] | 5.5 V |
| Voltage - Output (Min/Fixed) | Tracking |
| Voltage - Output (Min/Fixed) | 3.3 V |
| Voltage Dropout (Max) [Max] | 0.4 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.99 | |
| Digi-Reel® | 1 | $ 2.99 | ||
| Tape & Reel (TR) | 5000 | $ 2.26 | ||
| Microchip Direct | T/R | 1 | $ 2.99 | |
| 25 | $ 2.49 | |||
| 100 | $ 2.26 | |||
| 1000 | $ 2.19 | |||
| 5000 | $ 2.16 | |||
| Newark | Each (Supplied on Full Reel) | 1 | $ 2.33 | |
| 6000 | $ 2.33 | |||
Description
General part information
MIC68200 Series
The MIC68200 is a high peak-current LDO regulator designed specifically for powering applications such as FPGA core voltages that require high start up current with lower nominal operating current. The MIC68200 can also implement a variety of power-up and power-down protocols such as sequencing, tracking, and ratiometric tracking.
The MIC68200 operates from a wide input range of 1.65V to 5.5V, which includes all of the main supply voltages commonly available today. It is designed to drive digital circuits, requiring low voltage at high currents (i.e. PLDs, DSP, microcontroller, etc.). The MIC68200 incorporates a delay pin (Delay) for control of power-on reset (POR) output at turn-on and power-down delay at turn-off. In addition, there is a ramp control (RC) pin for either tracking applications or output voltage slew rate adjustment at turn-on and turn-off. This is important in applications where the load is highly capacitive and in-rush currents can cause supply voltages to fail and microprocessors or other complex logic chips to hang up.
Multiple MIC68200s can be daisy-chained in two modes. In tracking mode, the output voltage of the Master drives the RC pin of a Slave so that the Slave tracks the main regulator during turn-on and turn-off. In sequencing mode, the POR of the Master drives the enable (EN) of the Slave so that it turns on after the Master and turns off before (or after) the Master. This behavior is critical for power-up and power-down control in multi-output power supplies. The MIC68200 is fully protected, offering both thermal and current limit protection and reverse current protection.
Documents
Technical documentation and resources
