
ZL30256LFG7
ActiveDUAL CHANNEL JITTER ATTENUATOR 80 VFLGA 11X11X0.81MM TRAY ROHS COMPLIANT: YES
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ZL30256LFG7
ActiveDUAL CHANNEL JITTER ATTENUATOR 80 VFLGA 11X11X0.81MM TRAY ROHS COMPLIANT: YES
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | ZL30256LFG7 |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Divider/Multiplier | Yes/No |
| Frequency - Max [Max] | 1.045 GHz |
| Input | CMOS |
| Mounting Type | Surface Mount |
| Number of Circuits | 3 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 80-VFLGA |
| PLL | True |
| Ratio - Input:Output [custom] | 18 |
| Ratio - Input:Output [custom] | 10 |
| Supplier Device Package | 80-LGA (11x11) |
| Type | Jitter Attenuator |
| Voltage - Supply [Max] | 1.89 V, 3.465 V |
| Voltage - Supply [Min] | 3.135 V, 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 32.65 | |
| 25 | $ 27.20 | |||
| Microchip Direct | TRAY | 1 | $ 32.65 | |
| 25 | $ 27.20 | |||
| 100 | $ 24.75 | |||
| 1000 | $ 22.86 | |||
| 5000 | $ 21.68 | |||
| Newark | Each | 100 | $ 24.75 | |
Description
General part information
ZL30256 Series
[CREATE AND SAMPLE YOUR CUSTOM ZL30256 HERE](https://clockworks.microchip.com/microchip/design/inputZL)
The ZL30256 is multi-channel high-performance, any-rate multiplier and jitter attenuator which simplifies board design by generating ultra-low-jitter clock signals from or attenuating clock signals while generating additional independent frequency families. With 3 independent jitter attenuating DPLL channels, the ability to create 5 different frequency families and best-in-class jitter performance, the ZL30256 can create complete clock-trees, improving design reliability, reducing bill of materials (BOM) cost, and simplifying design by replacing multiple PLLs and peripheral timing components.
Documents
Technical documentation and resources