SN74AUC08RGYR
Active4-CH, 2-INPUT 0.8-V TO 2.7-V ULTRA-HIGH-SPEED (2.4 NS) AND GATE
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SN74AUC08RGYR
Active4-CH, 2-INPUT 0.8-V TO 2.7-V ULTRA-HIGH-SPEED (2.4 NS) AND GATE
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AUC08RGYR |
|---|---|
| Current - Output High, Low | 9 mA |
| Current - Quiescent (Max) [Max] | 10 µA |
| Input Logic Level - High [x] | 1.7 V |
| Input Logic Level - Low [Max] | 0.7 V |
| Input Logic Level - Low [Min] | 0 V |
| Logic Type | AND Gate |
| Max Propagation Delay @ V, Max CL | 1.8 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 4 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 14-VFQFN Exposed Pad |
| Supplier Device Package | 3.5x3.5, 14-VQFN |
| Voltage - Supply [Max] | 2.7 V |
| Voltage - Supply [Min] | 0.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.91 | |
| 10 | $ 0.80 | |||
| 25 | $ 0.75 | |||
| 100 | $ 0.61 | |||
| 250 | $ 0.57 | |||
| 500 | $ 0.48 | |||
| 1000 | $ 0.39 | |||
| Digi-Reel® | 1 | $ 0.91 | ||
| 10 | $ 0.80 | |||
| 25 | $ 0.75 | |||
| 100 | $ 0.61 | |||
| 250 | $ 0.57 | |||
| 500 | $ 0.48 | |||
| 1000 | $ 0.39 | |||
| N/A | 8520 | $ 0.84 | ||
| 83000 | $ 0.84 | |||
| Tape & Reel (TR) | 3000 | $ 0.30 | ||
| Mouser | N/A | 1 | $ 0.74 | |
| 10 | $ 0.53 | |||
| 25 | $ 0.47 | |||
| 100 | $ 0.42 | |||
| 250 | $ 0.37 | |||
| 1000 | $ 0.36 | |||
| 3000 | $ 0.30 | |||
| 9000 | $ 0.30 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.59 | |
| 100 | $ 0.45 | |||
| 250 | $ 0.33 | |||
| 1000 | $ 0.24 | |||
Description
General part information
74AUC08 Series
This quadruple 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
The SN74AUC08 device performs the Boolean function Y = A • B or Y = A • B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Documents
Technical documentation and resources
