
SN74ACT16374QDLREP
ActiveENHANCED PRODUCT 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
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SN74ACT16374QDLREP
ActiveENHANCED PRODUCT 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ACT16374QDLREP |
|---|---|
| Clock Frequency | 65 MHz |
| Current - Output High, Low [custom] | 16 mA |
| Current - Output High, Low [custom] | 16 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Function | Standard |
| Input Capacitance | 4.5 pF |
| Max Propagation Delay @ V, Max CL | 10.9 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 48-BSSOP |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 48-SSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 5.70 | |
| 10 | $ 5.12 | |||
| 25 | $ 4.84 | |||
| 100 | $ 4.20 | |||
| 250 | $ 3.98 | |||
| 500 | $ 3.57 | |||
| Digi-Reel® | 1 | $ 5.70 | ||
| 10 | $ 5.12 | |||
| 25 | $ 4.84 | |||
| 100 | $ 4.20 | |||
| 250 | $ 3.98 | |||
| 500 | $ 3.57 | |||
| Tape & Reel (TR) | 1000 | $ 3.01 | ||
| 2000 | $ 2.86 | |||
| Texas Instruments | LARGE T&R | 1 | $ 4.51 | |
| 100 | $ 3.67 | |||
| 250 | $ 2.89 | |||
| 1000 | $ 2.45 | |||
Description
General part information
SN74ACT16374-EP Series
The SN54ACT16374 and 74ACT16374 are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
An output-enable input (OE) can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system without need for interface or pullup components.OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Documents
Technical documentation and resources