Specification	SN74ACT574NSR

Clock Frequency	110 MHz
Current - Output High, Low	24 mA
Current - Quiescent (Iq)	4 çA
Function	Standard
Input Capacitance	4.5 pF
Max Propagation Delay @ V, Max CL	11 ns
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	20-SOIC
Package / Case	0.209 "
Package / Case	5.3 mm
Supplier Device Package	20-SO
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

CD74ACT574 Series

Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs

Part	Number of Bits per Element	Supplier Device Package	Trigger Type	Mounting Type	Clock Frequency	Input Capacitance	Max Propagation Delay @ V, Max CL	Function	Output Type	Number of Elements	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low	Current - Quiescent (Iq)	Type	Package / Case [y]	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN74ACT574NSRE4	8	20-SO	Positive Edge	Surface Mount	110 MHz	4.5 pF	11 ns	Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-SOIC	0.209 "	5.3 mm	85 °C	-40 °C	24 mA	4 çA	D-Type
Texas Instruments SN74ACT574DW	8	20-SOIC	Positive Edge	Surface Mount	110 MHz	4.5 pF	11 ns	Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-SOIC			85 °C	-40 °C	24 mA	4 çA	D-Type	0.295 in	7.5 mm
Texas Instruments CD74ACT574E	8	20-PDIP	Positive Edge	Through Hole	110 MHz	10 pF		Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-DIP	0.3 in	7.62 mm			24 mA	8 ÁA	D-Type			125 °C	-55 °C
Texas Instruments SN74ACT574DBR	8	20-SSOP	Positive Edge	Surface Mount	110 MHz	4.5 pF	11 ns	Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-SSOP			85 °C	-40 °C	24 mA	4 çA	D-Type
Texas Instruments SN74ACT574NG4	8	20-PDIP	Positive Edge	Through Hole	110 MHz	4.5 pF	11 ns	Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-DIP	0.3 in	7.62 mm	85 °C	-40 °C	24 mA	4 çA	D-Type
Texas Instruments SN74ACT574DWR	8	20-SOIC	Positive Edge	Surface Mount	110 MHz	4.5 pF	11 ns	Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-SOIC			85 °C	-40 °C	24 mA	4 çA	D-Type	0.295 in	7.5 mm
Texas Instruments SN74ACT574NS
Texas Instruments CD74ACT574EG4	8	20-PDIP	Positive Edge	Through Hole	110 MHz	10 pF		Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-DIP	0.3 in	7.62 mm			24 mA	8 ÁA	D-Type			125 °C	-55 °C
Texas Instruments CD74ACT574M96	8	20-SOIC	Positive Edge	Surface Mount	110 MHz	10 pF		Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-SOIC					24 mA	8 ÁA	D-Type	0.295 in	7.5 mm	125 °C	-55 °C
Texas Instruments SN74ACT574NSR	8	20-SO	Positive Edge	Surface Mount	110 MHz	4.5 pF	11 ns	Standard	Non-Inverted Tri-State	1	4.5 V	5.5 V	20-SOIC	0.209 "	5.3 mm	85 °C	-40 °C	24 mA	4 çA	D-Type

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 1.44
		10	$ 1.29
		25	$ 1.22
		100	$ 1.00
		250	$ 0.94
		500	$ 0.83
		1000	$ 0.65
	Digi-Reel®	1	$ 1.44
		10	$ 1.29
		25	$ 1.22
		100	$ 1.00
		250	$ 0.94
		500	$ 0.83
		1000	$ 0.65
	Tape & Reel (TR)	2000	$ 0.61
		6000	$ 0.58
		10000	$ 0.56
Texas Instruments	LARGE T&R	1	$ 1.07
		100	$ 0.82
		250	$ 0.60
		1000	$ 0.43

Description

General part information

CD74ACT574 Series

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

Documents

Technical documentation and resources

Datasheet

SN74ACT574NSR

Deep-Dive with AI

SN74ACT574NSR

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Technical Specifications

CD74ACT574 Series

Pricing

Description

CD74ACT574 Series

Documents

Datasheet

LOGIC Pocket Data Book (Rev. B)

Designing With Logic (Rev. C)

Implications of Slow or Floating CMOS Inputs (Rev. E)

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up Behavior of Clocked Devices (Rev. B)

Selecting the Right Level Translation Solution (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Logic Guide (Rev. AB)

CD74ACT574 Series