ZL30106QDG1
ActiveSONET/SDH/PDH NETWORK INTERFACE 64-PIN TQFP
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ZL30106QDG1
ActiveSONET/SDH/PDH NETWORK INTERFACE 64-PIN TQFP
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | ZL30106QDG1 |
|---|---|
| Differential - Input:Output | False |
| Frequency - Max [Max] | 65.536 MHz |
| Input | Crystal, Clock |
| Main Purpose | SDH, PDH, SONET |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | Clock |
| Package / Case | 64-TQFP |
| PLL | True |
| Ratio - Input:Output [custom] | 12 |
| Ratio - Input:Output [custom] | 3 |
| Supplier Device Package | 64-TQFP (10x10) |
| Voltage - Supply [Max] | 3.63 V |
| Voltage - Supply [Min] | 2.97 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 160 | $ 36.79 | |
| Microchip Direct | TRAY | 1 | $ 45.71 | |
| 25 | $ 38.08 | |||
| 100 | $ 34.63 | |||
| 1000 | $ 32.02 | |||
| 5000 | $ 30.35 | |||
Description
General part information
ZL30106 Series
The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.
The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.
The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.
Documents
Technical documentation and resources