CY74FCT823CTSOC
Active9-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
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CY74FCT823CTSOC
Active9-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | CY74FCT823CTSOC |
|---|---|
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Current - Quiescent (Iq) | 200 µA |
| Input Capacitance | 5 pF |
| Max Propagation Delay @ V, Max CL | 12.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 9 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 24-SOIC |
| Package / Case [custom] | 7.5 mm |
| Package / Case [custom] | 0.295 in |
| Supplier Device Package | 24-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.96 | |
| 10 | $ 0.86 | |||
| 25 | $ 0.81 | |||
| 100 | $ 0.67 | |||
| 250 | $ 0.63 | |||
| 500 | $ 0.55 | |||
| Texas Instruments | TUBE | 1 | $ 0.71 | |
| 100 | $ 0.55 | |||
| 250 | $ 0.40 | |||
| 1000 | $ 0.29 | |||
Description
General part information
CY74FCT823T Series
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Documents
Technical documentation and resources
