CY74FCT823T Series

9-Bit Bus Interface Flip-Flops with 3-State Outputs

Catalog

9-Bit Bus Interface Flip-Flops with 3-State Outputs

Part	Type	Output Type	Number of Bits per Element	Mounting Type	Number of Elements	Package / Case	Package / Case	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Quiescent (Iq)	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Input Capacitance	Trigger Type	Max Propagation Delay @ V, Max CL	Package / Case [custom]	Package / Case [custom]
Texas Instruments CY74FCT823ATPC	D-Type	Non-Inverted Tri-State	9	Through Hole	1	0.3 in	24-DIP	7.62 mm	85 °C	-40 °C	64 mA	32 mA	200 µA	24-PDIP	4.75 V	5.25 V	5 pF	Positive Edge	20 ns
Texas Instruments CY74FCT823CTSOC	D-Type	Non-Inverted Tri-State	9	Surface Mount	1		24-SOIC		85 °C	-40 °C	64 mA	32 mA	200 µA	24-SOIC	4.75 V	5.25 V	5 pF	Positive Edge	12.5 ns	7.5 mm	0.295 in
Texas Instruments CY74FCT823CTQC
Texas Instruments CY74FCT823ATQCT	D-Type	Non-Inverted Tri-State	9	Surface Mount	1		24-SSOP		85 °C	-40 °C	64 mA	32 mA	200 µA	24-SSOP	4.75 V	5.25 V	5 pF	Positive Edge	20 ns	0.154 " 3.9 mm
Texas Instruments CY74FCT823CTSOCT	D-Type	Non-Inverted Tri-State	9	Surface Mount	1		24-SOIC		85 °C	-40 °C	64 mA	32 mA	200 µA	24-SOIC	4.75 V	5.25 V	5 pF	Positive Edge	12.5 ns	7.5 mm	0.295 in
Texas Instruments CY74FCT823ATSOC	D-Type	Non-Inverted Tri-State	9	Surface Mount	1		24-SOIC		85 °C	-40 °C	64 mA	32 mA	200 µA	24-SOIC	4.75 V	5.25 V	5 pF	Positive Edge	20 ns	7.5 mm	0.295 in

Catalog

9-Bit Bus Interface Flip-Flops with 3-State Outputs

Key Features

• Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823Reduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)64-mA Output Sink Current32-mA Output Source CurrentHigh-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-FlopsBuffered Common Clock-Enable (EN\) and Asynchronous-Clear (CLR\) Inputs3-State OutputsFunction, Pinout, and Drive Compatible With FCT, F Logic, and AM29823Reduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)64-mA Output Sink Current32-mA Output Source CurrentHigh-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-FlopsBuffered Common Clock-Enable (EN\) and Asynchronous-Clear (CLR\) Inputs3-State Outputs

Description

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.