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Integrated Circuits (ICs)

SN74LV595BMPWREP

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Texas Instruments

ENHANCED PRODUCT EIGHT-BIT SHIFT REGISTERS WITH TRI-STATE OUTPUT REGISTERS

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TSSOP (PW)
Integrated Circuits (ICs)

SN74LV595BMPWREP

Active
Texas Instruments

ENHANCED PRODUCT EIGHT-BIT SHIFT REGISTERS WITH TRI-STATE OUTPUT REGISTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LV595BMPWREP
FunctionSerial to Parallel, Serial
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 2.23
10$ 2.01
25$ 1.89
100$ 1.61
250$ 1.51
500$ 1.33
1000$ 1.10
Digi-Reel® 1$ 2.23
10$ 2.01
25$ 1.89
100$ 1.61
250$ 1.51
500$ 1.33
1000$ 1.10
Tape & Reel (TR) 3000$ 1.02
6000$ 0.98
Texas InstrumentsLARGE T&R 1$ 1.68
100$ 1.39
250$ 1.00
1000$ 0.75

Description

General part information

SN74LV595B-EP Series

The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.

The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.