Specification	SN74LVC2G80DCTR

Clock Frequency	160 MHz
Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	5 µA
Function	Standard
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	4.5 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	1.81 mOhm
Supplier Device Package	SM8
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC2G80 Series

Dual Positive-Edge-Triggered D-Type Flip-Flop

Part	Output Type	Function	Number of Bits per Element	Trigger Type	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [y]	Current - Output High, Low [x]	Package / Case [y]	Package / Case	Package / Case [y]	Clock Frequency	Current - Quiescent (Iq)	Number of Elements	Max Propagation Delay @ V, Max CL	Input Capacitance	Type	Supplier Device Package
Texas Instruments SN74LVC2G80DCUR	1.81 mOhm	Standard	1	Positive Edge	-40 °C	125 °C	Surface Mount	5.5 V	1.65 V	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in	160 MHz	5 µA	2	4.5 ns	3.5 pF	D-Type
Texas Instruments SN74LVC2G80DCTR	1.81 mOhm	Standard	1	Positive Edge	-40 °C	125 °C	Surface Mount	5.5 V	1.65 V	32 mA	32 mA				160 MHz	5 µA	2	4.5 ns	3.5 pF	D-Type	SM8
Texas Instruments SN74LVC2G80DCURG4	1.81 mOhm	Standard	1	Positive Edge	-40 °C	125 °C	Surface Mount	5.5 V	1.65 V	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in	160 MHz	5 µA	2	4.5 ns	3.5 pF	D-Type
Texas Instruments SN74LVC2G80DCTRG4	1.81 mOhm	Standard	1	Positive Edge	-40 °C	125 °C	Surface Mount	5.5 V	1.65 V	32 mA	32 mA				160 MHz	5 µA	2	4.5 ns	3.5 pF	D-Type	SM8
Texas Instruments SN74LVC2G80YZPR	1.81 mOhm	Standard	1	Positive Edge	-40 °C	85 °C	Surface Mount	5.5 V	1.65 V	32 mA	32 mA		8-XFBGA DSBGA		160 MHz	5 µA	2	4.5 ns	3.5 pF	D-Type	8-DSBGA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.81
		10	$ 0.72
		25	$ 0.67
		100	$ 0.55
		250	$ 0.51
		500	$ 0.43
		1000	$ 0.35
	Digi-Reel®	1	$ 0.81
		10	$ 0.72
		25	$ 0.67
		100	$ 0.55
		250	$ 0.51
		500	$ 0.43
		1000	$ 0.35
	Tape & Reel (TR)	3000	$ 0.27
Texas Instruments	LARGE T&R	1	$ 0.56
		100	$ 0.38
		250	$ 0.29
		1000	$ 0.19

Description

General part information

SN74LVC2G80 Series

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Documents

Technical documentation and resources

SN74LVC2G80DCTR

Deep-Dive with AI

SN74LVC2G80DCTR

Deep-Dive with AI

Technical Specifications

SN74LVC2G80 Series

Pricing

Description

SN74LVC2G80 Series

Documents

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

How to Select Little Logic (Rev. A)

Power-Up Behavior of Clocked Devices (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Little Logic Guide 2018 (Rev. G)

Input and Output Characteristics of Digital Integrated Circuits

LOGIC Pocket Data Book (Rev. B)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Dual Positive-Edge-Triggered D-Type Flip-Flop, SN74LVC2G80 datasheet (Rev. F)

Signal Switch Data Book (Rev. A)

Live Insertion

Logic Guide (Rev. AB)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Standard Linear & Logic for PCs, Servers & Motherboards

Texas Instruments Little Logic Application Report

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

CMOS Power Consumption and CPD Calculation (Rev. B)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

LVC Characterization Information

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Selecting the Right Level Translation Solution (Rev. A)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Low-Voltage Logic (LVC) Designer's Guide

Understanding Advanced Bus-Interface Products Design Guide

Design Summary for WCSP Little Logic (Rev. B)

SN74LVC2G80 Series