Texas Instruments-THS7368IPWR Video Amplifiers Video Amp Hex 5V 20-Pin TSSOP T/R

Integrated Circuits (ICs)

SN74LVT240APW

Active

8-CH, 2.7-V TO 3.6-V INVERTERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsBus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)+14

Integrated Circuits (ICs)

SN74LVT240APW

Active

Texas Instruments

8-CH, 2.7-V TO 3.6-V INVERTERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsBus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)+14

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVT240APW

Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Logic Type	Inverting, Buffer
Mounting Type	Surface Mount
Number of Bits per Element	4
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	3-State
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVT240A Series

8-ch, 2.7-V to 3.6-V inverters with TTL-compatible CMOS inputs and 3-state outputs

Part	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Package / Case	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Logic Type	Output Type	Number of Bits per Element	Package / Case	Package / Case	Package / Case [y]	Package / Case [y]	Package / Case [x]
Texas Instruments SN74LVT240ADBR	20-SSOP	2.7 V	3.6 V	85 °C	-40 °C	2	20-SSOP	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4
Texas Instruments SN74LVT240ANSR	20-SO	2.7 V	3.6 V	85 °C	-40 °C	2	20-SOIC	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4	0.209 "	5.3 mm
Texas Instruments SN74LVT240ADW	20-SOIC	2.7 V	3.6 V	85 °C	-40 °C	2	20-SOIC	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4			0.295 in	7.5 mm
Texas Instruments SN74LVT240ADWR	20-SOIC	2.7 V	3.6 V	85 °C	-40 °C	2	20-SOIC	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4			0.295 in	7.5 mm
Texas Instruments SN74LVT240APWRE4	20-TSSOP	2.7 V	3.6 V	85 °C	-40 °C	2	20-TSSOP	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4			4.4 mm		0.173 in
Texas Instruments SN74LVT240APWG4	20-TSSOP	2.7 V	3.6 V	85 °C	-40 °C	2	20-TSSOP	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4			4.4 mm		0.173 in
Texas Instruments SN74LVT240APW	20-TSSOP	2.7 V	3.6 V	85 °C	-40 °C	2	20-TSSOP	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4			4.4 mm		0.173 in
Texas Instruments SN74LVT240APWR	20-TSSOP	2.7 V	3.6 V	85 °C	-40 °C	2	20-TSSOP	Surface Mount	64 mA	32 mA	Buffer Inverting	3-State	4			4.4 mm		0.173 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Arrow	N/A	1050	$ 0.48
Digikey	Tube	1	$ 1.36
		10	$ 1.21
		70	$ 1.15
		140	$ 0.95
		280	$ 0.88
		560	$ 0.78
		1050	$ 0.62
		2520	$ 0.58
		5040	$ 0.55
Texas Instruments	TUBE	1	$ 1.00
		100	$ 0.77
		250	$ 0.57
		1000	$ 0.41

Description

General part information

SN74LVT240A Series

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Documents

Technical documentation and resources

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

SN74LVT240APW

Deep-Dive with AI

SN74LVT240APW

Deep-Dive with AI

Technical Specifications

SN74LVT240A Series

Pricing

Description

SN74LVT240A Series

Documents

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

SN74LVT240A datasheet (Rev. K)

Live Insertion

LOGIC Pocket Data Book (Rev. B)

LVT-to-LVTH Conversion

Input and Output Characteristics of Digital Integrated Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

Advanced Bus Interface Logic Selection Guide

Logic Guide (Rev. AB)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

LVT Family Characteristics (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Understanding Advanced Bus-Interface Products Design Guide

SN74LVT240A Series