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Technical Specifications
Parameters and characteristics for this part
| Specification | DAC161S055CISQX |
|---|---|
| Architecture | R-2R |
| Data Interface | SPI |
| Differential Output | False |
| INL/DNL (LSB) | 1 LSB |
| INL/DNL (LSB) [Max] | 1.1 LSB |
| Mounting Type | Surface Mount |
| Number of Bits | 16 |
| Operating Temperature [Max] | 105 ░C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Buffered |
| Package / Case | 16-WFQFN Exposed Pad |
| Reference Type | External |
| Settling Time | 5 µs |
| Supplier Device Package | 16-WQFN (4x4) |
| Voltage - Supply, Analog [Max] | 5.25 V |
| Voltage - Supply, Analog [Min] | 2.7 V |
| Voltage - Supply, Digital [Max] | 5.25 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
DAC161S055 Series
The DAC161S055 is a precision 16-bit, buffered voltage output Digital-to-Analog Converter (DAC) that operates from a 2.7V to 5.25V supply with a separate I/O supply pin that operates down to 1.7V. The on-chip precision output buffer provides rail-to-rail output swing and has a typical settling time of 5 µsec. The external voltage reference can be set between 2.5V and VA(the analog supply voltage), providing the widest dynamic output range possible.
The 4-wire SPI compatible interface operates at clock rates up to 20 MHz. The part is capable of Diasy Chain and Data Read Back. An on board power-on-reset (POR) circuit ensures the output powers up to a known state.
The DAC161S055 features a power-up value pin (MZB), a load DAC pin (LDACB) and a DAC clear (CLRB) pin. MZB sets the startup output voltage to either GND or mid-scale. LDACB updates the output, allowing multiple DACs to update their outputs simultaneously. CLRB can be used to reset the output signal to the value determined by MZB.
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