Specification	ADSP-21363BSWZ-1AA

Interface	SPI, DAI
Mounting Type	Surface Mount
Non-Volatile Memory	512 kB
On-Chip RAM	384 kB
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	144-LQFP Exposed Pad
Supplier Device Package	144-LQFP-EP (20x20)
Type	Floating Point
Voltage - Core	1.2 V
Voltage - I/O	3.3 V

ADSP-21363 Series

Part	Clock Rate	Non-Volatile Memory	Type	Voltage - Core [custom]	Voltage - I/O	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Interface	Package / Case	Supplier Device Package	On-Chip RAM	Voltage - Core
Analog Devices ADSP-21363YSQZ-2AA	200 MHz	512 kB	Fixed/Floating Point	1 V	3.3 V	-40 °C	105 ░C	Surface Mount	DAI SPI	144-LQFP Exposed Pad	144-LQFP (20x20)	384 kB
Analog Devices ADSP-21363KBC-1AA		512 kB	Floating Point		3.3 V	0 °C	70 °C	Surface Mount	DAI SPI	136-LFBGA CSPBGA	136-CSPBGA (12x12)	384 kB	1.2 V
Analog Devices ADSP-21363BSWZ-1AA		512 kB	Floating Point		3.3 V	-40 °C	85 °C	Surface Mount	DAI SPI	144-LQFP Exposed Pad	144-LQFP-EP (20x20)	384 kB	1.2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	1	$ 74.59
		10	$ 58.98
		25	$ 54.99
		80	$ 52.61

Description

General part information

ADSP-21363 Series

The third generation of SHARC®Processors, which includes theADSP-21261,ADSP-21262,ADSP-21266, ADSP-21363,ADSP-21364,ADSP-21365, andADSP-21366offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21363 offers the highest performance – 333 MHz/2 GFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21363 particularly well suited to address the increasing requirements of many general purpose signal processing applications.Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include, but are not limited to, serial ports, SPI ports and an 8-Channel asynchronous sample rate converter block.

Documents

Technical documentation and resources

ADSP-21363BSWZ-1AA

Deep-Dive with AI

ADSP-21363BSWZ-1AA

Deep-Dive with AI

Technical Specifications

ADSP-21363 Series

Pricing

Description

ADSP-21363 Series

Documents

An Almost Pure DDS Sine Wave Tone Generator

Datasheet

EE-277: Estimating Power for the ADSP-21362 SHARC® Processors (Rev.1)

EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)

EE-128: DSP in C++: Calling Assembly Class Member Functions From C++

VisualDSP++®5.0 Getting Started Guide (Rev.3.0)

EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)

VisualDSP++®5.0 Product Release Bulletin (Rev.3.0)

EE-104: Setting Up Streams with the VisualDSP Debugger

ICE-100B Emulator User’s Guide (Rev.1.1)

EE-290: Managing the Core PLL on SHARC® Processors (Rev.5)

Blackfin®/SHARC®USB EZ-Extender®Manual (Rev.1.1)

EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)

EE-110: A Quick Primer on ELF and DWARF File Formats

ICE-1000/ICE-2000 Emulator User’s Guide (Rev.1.2)

SHARC®Processor Programming Reference (Includes ADSP-2136x, ADSP-2137x, and ADSP-214xx Processors) (Rev.2.4)

SHARC®USB EZ-Extender®Manual (Rev.2.1)

EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs

VisualDSP++®5.0 Run-Time Library Manual for SHARC®Processors (Rev.1.5)

EE-320: Implementing an Ogg Vorbis Decoder on SHARC® Processors (Rev.1)

EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev.1)

EE-254: Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (Rev.1)

EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)

VisualDSP++®5.0 Quick Installation Reference Card (Rev.3.1)

VisualDSP++®5.0 Licensing Guide (Rev.1.4)

EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev.1)

EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)

EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs

EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev.1)

EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev.3)

ADSP-2136x SHARC®Processor Hardware Reference (includes the ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 processors) (Rev.2.1)

EE-305: Designing and Debugging Systems with SHARC Processors (Rev.1)

EE-332: Cycle Counting and Profiling (Rev.2)

EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)

SHARC®Audio EZ-Extender®Manual (Rev.1.1)

EE-340: Connecting SHARC®and Blackfin®Processors over SPI (Rev.1)

EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev.1)

VisualDSP++®5.0 Linker and Utilities Manual (Rev.3.5)

EE-260: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (Rev.1)

SHARC®EZ-Extender®Manual (Rev.3.1)

EE-266: Programming S/PDIF on ADSP-2136x and ADSP-21371 SHARC® Processors (Rev.2)

EE-231: In-Circuit Programming of an SPI Flash with SHARC® Processors (Rev.2)

Package Drawing - 144-Lead LQFP (10mm x 10mm w/ EP)

EE-220: Using External Memory with Third Generation SHARC® Processors and the Parallel Port (Rev.2)

EE-295: Implementing Delay Lines on SHARC® Processors (Rev.1)

EE-248: Interfacing AD7676 ADCs to ADSP-21365 SHARC® Processors (Rev.1)

EE-345: Boot Kernel Customization and Firmware Upgradeability on SHARC Processors® (Rev.1)

VisualDSP++®5.0 Loader and Utilities Manual (Rev.2.5)

EE-268: Programming Asynchronous Sample Rate Converters on ADSP-2136x SHARC® Processors (Rev.1)

EE-296: Using the UART Port Controller on SHARC® Processors (Rev.2)

VisualDSP++®5.0 Users Guide (Rev.3.0)

EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev.2)

EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)

EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev.1)

HPUSB, USB, and HPPCI Emulator User’s Guide (Rev.3.2)

VisualDSP++®5.0 C/C++ Compiler Manual for SHARC®Processors (Rev.1.5)

VisualDSP++®5.0 Assembler and Preprocessor Manual (Rev.3.4)

EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)

EE-177: SHARC® SPI Slave Booting (Rev.3)

SHARC Processor Family

EE-322: Expert Code Generator for SHARC® Processors (Rev.5)

EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)

EE-230: Code Overlays on the Third Generation SHARC® Family of Processors (Rev.2)

VisualDSP++®5.0 Kernel (VDK) Users Guide (Rev.3.5)

ADSP-21363 Series