CD54HC597F3A
ActiveHIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE
Deep-Dive with AI
Search across all available documentation for this part.
CD54HC597F3A
ActiveHIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC597F3A |
|---|---|
| Function | Parallel or Serial to Serial |
| Logic Type | Shift Register |
| Mounting Type | Through Hole |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Non-Inverted |
| Package / Case | 7.62 mm, 0.3 in |
| Package / Case | 16-CDIP |
| Supplier Device Package | 16-CDIP |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 60.95 | |
| 100 | $ 54.18 | |||
| 250 | $ 44.54 | |||
| 1000 | $ 39.84 | |||
Description
General part information
CD54HC597 Series
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
Documents
Technical documentation and resources