ZL40220LDG1
ActiveCLOCK BUFFER, FANOUT, 750 MHZ, 6 OUTPUTS, 3.135 V TO 3.465 V, 32 PINS, QFN-EP
Deep-Dive with AI
Search across all available documentation for this part.
ZL40220LDG1
ActiveCLOCK BUFFER, FANOUT, 750 MHZ, 6 OUTPUTS, 3.135 V TO 3.465 V, 32 PINS, QFN-EP
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | ZL40220LDG1 |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 750 MHz |
| Input | LVCMOS, HCSL, CML, LVDS, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVDS |
| Package / Case | 32-VFQFN Exposed Pad |
| Ratio - Input:Output [custom] | 6 |
| Ratio - Input:Output [custom] | 2 |
| Supplier Device Package | 32-QFN (5x5) |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 490 | $ 5.14 | |
| Microchip Direct | TRAY | 1 | $ 6.37 | |
| 25 | $ 5.31 | |||
| 100 | $ 4.83 | |||
| 1000 | $ 4.47 | |||
| 5000 | $ 4.24 | |||
| Newark | Each | 100 | $ 4.83 | |
Description
General part information
ZL40220 Series
The ZL40220 is an LVDS clock fanout buffer with six identical output clock drivers capable of operating at frequencies up to 750MHz.
The two Inputs to the ZL40220 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40220 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.
The ZL40220 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. It's operation is guaranteed over the industrial temperature range -40°C to +85°C.
Documents
Technical documentation and resources